The present invention relates to a graphic processing apparatus for displaying and printing out characters and graphics, and in particular, to a graphic processing apparatus capable of effecting a drawing processing at a high speed not only in a frame buffer but also in a system memory (main memory).
There has been a method (called a bit map method) to display characters and graphics on a CRT screen according to a raster scan method by use of a memory (bit map memory) storing information associated with each pixel of the display apparatus. Furthermore, this method including the bit map memory has also been applied to a case where control is effected to output data to a printer. Conventionally, processing to generate characters and graphic data in the bit map memory is primarily achieved by means of the software; however, there has arisen a problem that the processing speed is low because of a great amount of data to be processed. On the other hand, particularly, in a field where graphic forms are to be generated at a high speed, there has been partly used a method including dedicated hardware, which is however attended with a disadvantage that the cost of the graphic processing apparatus is increased.
To cope with such a situation, the function to generate characters and graphic data has become to be integrated in an LSI chip. Such an LSI has been proposed in the xe2x80x9cCRT Controller Having a Plenty of Commands Such As Paint Out and Copy and Enabling to Specify Drawing Position by Coordinatesxe2x80x9d written by Kazuo Minorikawa in the xe2x80x9cNikkei Electronicsxe2x80x9d, May 21, 1984, pp. 221-254; and in the U.S. Ser. Nos. 686,039 and 727,850. This LSI enables to greatly increase the speed of the graphic processing at a relatively low cost.
According to the paper above, the drawing processing can be executed in a frame buffer at a high speed; however, the drawing processing cannot be achieved in a system memory (main memory) connected to a CPU.
For example, other output means such as a control circuit of a printer is connected to a system bus in many cases, where a buffer for use with a print operation is reserved in the system memory. At the present stage of technology, in the case where graphic data is to be outputted to a printer, since the drawing operation cannot be accomplished by the CRT controller above, the drawing is effected by the software. As a result, though the graphic data to be displayed in the CRT screen is drawn at a high speed, the drawing of the graphic data to be outputted to a printer is executed at a low speed.
On the other hand, it can be considered as means to improve the processing performance, to subdivide the frame buffer in color plane units, thereby effecting a concurrent processing by use of a plurality of graphic processors. According to the method described in the papers above using the CRT controller, in order to achieve a copy processing of the same fundamental information (for example, font data of a character) onto a plurality of planes, it is necessary to beforehand store fundamental information in the frame buffer corresponding to the respective planes. Namely, the memory utilization efficiency is lowered because same information is arranged in a plurality of memories.
According to the prior art technology as described above, in addition to the low speed of the drawing operation in the system memory, a plurality of same information such as a character font must be provided in the case where the frame buffer is subdivided into color plane units to achieve a parallel processing thereon by a plurality of processors.
The JP-A-60-136793 has disclosed a graphic processing apparatus including a graphic generate function implemented as an LSI to achieve a graphic processing at a high speed by use of a bit map method. In the JP-A-60-136793, a plurality of pixel information are stored in a word of a memory, a predetermined word is read from the memory while an address identifying a pixel in sequence is being generated, particular pixel data is updated in the word, and the word data thus attained is written again in the word, thereby effecting a drawing operation. That is, the processing of a word is effected through a sequence of processing of a read operation, an arithmetic operation, and a write operation so as to achieve a drawing operation.
Furthermore, the JP-A-60-40588 describes a technology to write pixel information of a bit in a raster direction.
The JP-A-61-130991 (Japanese Patent Application No. 59-251907) has disclosed a graphic processing apparatus in which X and Y coordinates are calculated so as to effect a drawing operation while calculating an X-coordinate memory address corresponding to the attained coordinate values. According to the known example, the arithmetic unit to execute the coordinate calculation and an arithmetic unit to achieve the memory address calculation are controlled by a common microprogram.
In the xe2x80x9cLSI Handboodxe2x80x9d, OHM-Sha, Ltd., Nov. 30, 1984, page 556 and subsequent pages, there has been disclosed a method in which in consideration of the fact that when a relatively complex processing is required to be executed in a unit of a pixel like in a graphics processing, it is not necessarily advantageous in the improvement of the utilization efficiency of the processor and in the enhancement of the speed of the image processing to accomplish all processing by the microprocessor, the generation of basic graphic forms, the operation to paint out a graphic form, the drawing of lines, etc. are achieved by an apparatus such as a display controller dedicated to the image processing.
Incidentally, when a bold line is to be drawn by a line drawing command in the prior art image processing apparatus such as a display controller, a line having a width determined by a size of a pixel is required to be many times drawn to attain the bold line.
As a processor for a graphic controller, there has been known a processor described in pages 522-589 of the xe2x80x9cHitachi Microcomputer {fraction (8/16)}-Bit Microcomputer Peripheral LSIxe2x80x9d (HD63484) published from the Hitachi, Ltd. in Nov. 1985.
Representative drawing functions of the processor interpret and execute 38 kinds of graphic drawing commands, for example, to draw a line, to draw a circle, to paint a graphic form, to copy a graphic image, and the like. Moreover, the processor has several kinds of drawing and arithmetic operation modes. Particularly, when a conditional replacement is used, color drawing functions can be developed, for example, to specify a particular background color, to designate a drawing inhibit color, and to draw an image with a priority assigned to color data.
It is therefore an object of the present invention to provide a graphic processing system which enables the graphic processor to access the system memory so as to increase the speed of the drawing operation on the system memory and in which, when a parallel processing is executed by a plurality of processors, fundamental information such as a character font to be commonly used is located in the system memory so as to be shared among the processors.
Another object of the present invention is to provide a graphic processing apparatus in which processing of a pixel is accomplished on through a write operation so as to generate and to draw graphic data including a line, an arc, and the like.
Still another object of the present invention is to provide a graphic processing apparatus in which a microprogram to achieve the coordinate calculation and a microprogram to execute the memory address calculation are separated from each other so as to improve the describability or the describing capability of a program.
Further, another object of the present invention is to provide a graphic processing apparatus including a multi-way branch method improving the efficiency of a microprogram.
Another object of the present invention is to provide a graphic processing apparatus having an efficient method of debugging a microprogram in which a microprogram in execution is halted at a desired address, internal information of the graphic processing apparatus is read out, and thereafter the halted microprogram is restarted for the execution thereof.
Still another object of the present invention is to provide an graphic processing apparatus which is capable of effecting a drawing operation by use of as the basic unit a picture element (PEL), namely, a dot having an arbitrary shape and an arbitrary size configured in association with a plurality of picture cells (pixels).
Another object of the present invention is to provide an graphic processing apparatus in which during the drawing operation using the pel as the basic unit, a high-speed drawing operation and a drawing operation through a control effected on a pel region for a drawing area can be effected.
Another object of the present invention is to provide an image processing apparatus capable of achieving a data processing of a plurality of color pixel information in the unit of a word so as to increase the speed of the drawing processing.
According to a feature of the present invention, there is provided a graphic processing system having a graphic processor (GDP) which interprets a command transferred from a first data bus connected to a main processor (CPU) and effects an access (for example, a drawing) by use of a second address bus and a second data bus connected to a frame buffer. In the graphic processing system, there is provided bus connection control means capable of effecting a connection or a disconnection between the first address bus and the first data bus each connected to the main processor and the main memory and the second address bus and the second data bus each connected to the frame buffer.
In order to enable the graphic processor to achieve a drawing in the system memory, an address sent to the second address bus connected to the frame buffer is transferred via the bus connection control means and the first address bus to the system memory, and at the same time, the first data bus is connected to the second data bus so as to effect a data read/write operation requested by the GDP to read/write data in/from the system memory.
Furthermore, in a system including a plurality of graphic processors and a plurality of frame buffers for the respective color planes, the bus connection control means is controlled such that based on an address supplied from one of the graphic processors, basic information is read from the system memory and the obtained data is loaded in the processors at the same time. A high-speed drawing operation can be accomplished on the main memory by use of a second processor dedicated to the drawing operation.
According to a second feature of the present invention, drawing processor means which sequentially calculates drawing addresses and outputs drawing data so as to effect a drawing control outputs an address in word units together with information identifying pixels in a word, and then outputted information is interpreted by memory write control means, thereby achieving a write operation only in a portion of the memory corresponding to the identified pixels.
That is, the memory write control means generates a different write control signal for each memory element corresponding to each pixel of a word. The circuit configuration is implemented such that a write control signal is outputted for a word in the case of a write operation in the unit of a word, and a write control signal is delivered for a predetermined pixel in the case of a write operation in the unit of a pixel.
According to the third feature of the present invention, there is provided a drawing processing apparatus in which a microprogram to control the coordinate operation and a microprogram to control the memory address operation are separately arranged. The microprogram controlling the coordinate operation causes the microprogram controlling the memory address operation to operate and thereafter the microprogram controlling the memory address operation independently effects execution of the microprogram. When an operation request is issued during the operation of the microprogram controlling the memory address operation, there is used a means provided to cause the microprogram controlling the coordinate operation to stop the operation thereof until the processing of the microprogram controlling the memory address operation is finished.
According to another aspect of the features of the present invention there are provided means for storing information used to effect a multi-way branch in a microprogram controlling the coordinate operation and means for storing the number of the significant bits of said means such that when loading a jump address in an address register, only for the bits specified by the means storing the significant bit count, the data of means storing information of the multi-way branch is used in place of the jump address.
According to another aspect of the present invention, there are provided means for storing an address used to stop the microprogram controlling the coordinate operation and means for comparing the content of the means storing the stop address with an address of the microprogram so as to output a signal when a signal agreement results such that the agreement signal is used to set or reset the address register.
According to the third feature above, since the microprogram controlling the coordinate operation is separated from that controlling the memory address operation, the microprogram controlling the coordinate operation needs to only include a description of a drawing algorithm, which improves the descriptivity or the describing capability of the program.
The provisions of the means storing information to effect a multi-way branch in the microprogram and means indicating the significant bits of the means enable a variable number of branches to be specified.
Owing to the means comparing the content of the means storing an address to stop the microprogram with an address of the microprogram so as to output an agreement signal when a signal agreement results, a unique value can be generated and loaded in the address register of the microprogram in response to the agreement signal, thereby stopping the microprogram to effect a debug.
According to the outline of the fourth feature of the present invention, there is provided a graphic processing apparatus including pel data store means for storing pel data in the form of binary information asociated with a dot having an arbitrary shape and an arbitrary size configured corresponding to a plurality of pixels and arithmetic means for achieving a logic operation to draw data undergone a color development based on the pel data according to a position of the indication point of the current pointer.
According to the constitution described above, a predetermined pel data is selected from various pel data defined in the pel data store means so as to effect a logic operation to achieve a drawing operation depending on the position of the indication point of the current pointer, thereby accomplishing an efficient operation to draw a bold line.
According to the fifth feature of the present invention, on receiving information including a plurality of bits representing a character or a graphic form in which a pixel comprises a bit, a plurality of bits are extracted therefrom so as to be subjected to a color development by use of a barrel shifter, the attained bits are expanded into bit information equivalent to a plurality of color pixels corresponding to color pixels in which a pixel comprise N bits, and depending on said bit information, the contents of a first color register and a second color register holding color pixel information equivalent to the plurality of pixels each comprising N bits are selectively outputted. Furthermore, color pixel information of two words each including a plurality of color pixel information is stored in a source data register, pixel data is extracted in the word units in association with the destination data by use of a barrel shifter, a color operation comparison is achieved depending on a color compare mode on color information specified by a combination of an output signal from the barrel shifter and the destination data or a combination of the output signal from the barrel shifter and the color compare register and color information specified by the destination data and the color compare register, and then depending on the output signal and a predetermined color processing signal, write color pixel information in the unit of a word is generated from the output signal from the barrel shifter and the 1 destination data.